from machine import FPIOA
from machine import Pin
from machine import SPI
from machine import UART
import time

spi = FPIOA()
pin = FPIOA()
uart = FPIOA()


############################# SPI0 moudle1 Configure start ####################
pin.set_function(48, pin.GPIO48)
pin.set_function(49, pin.GPIO49)
#spi.set_function(14,spi.QSPI0_CS0)          #SPI1 CS
pin.set_function(14, pin.GPIO14)
spi.set_function(15,spi.QSPI0_CLK)          #SPI1 CLK
spi.set_function(16,spi.QSPI0_D0)           #SPI1 D0
spi.set_function(17,spi.QSPI0_D1)           #SPI1 D1

uart.set_function(11, uart.UART2_TXD)
uart.set_function(12, uart.UART2_RXD)

IRQ = Pin(48, Pin.IN, pull = Pin.PULL_NONE)                    #moudle1 irq
CE  = Pin(49, Pin.OUT, pull = Pin.PULL_NONE, drive = 7)        #moudle1 CE
CS  = Pin(14, Pin.OUT, pull = Pin.PULL_NONE, drive = 7)        #moudle1 CS
CS.high()

############################# SPI0 moudle1 Configure end ####################



module0 = SPI(1, baudrate = 10000000, polarity = 0, phase = 0, bits = 8)

uart2 = UART(UART.UART2, baudrate = 115200, bits=UART.EIGHTBITS, parity=UART.PARITY_NONE, stop=UART.STOPBITS_ONE)


def moduleWriteReg(dev, reg, regVal):
    data = bytearray(2)
    data[0] = 0x20 | reg
    data[1] = regVal

    CS.low()
    dev.write(data)
    CS.high()
    print("write reg:{0},value:{1}".format(hex(data[0]), hex(data[1])))

def moduleReadReg(dev, reg, readbuf):
    data = bytearray(2)
    data[0] = reg
    data[1] = 0xFF
    CS.low()
    dev.write_readinto(data, readbuf)
    CS.high()
    print("read reg:{0}, status:{1}, value:{2}".format(hex(data[0]), hex(readbuf[0]), hex(readbuf[1])))



def moduleWriteCmd(dev, opt, buf, len):
    data = bytearray(len + 1)
    i = 0
    while i < len + 1:
        if i == 0:
            data[i] = opt
        else:
            data[i] = buf[i - 1]
        i = i + 1
    CS.low()
    dev.write(data)
    CS.high()
    print("write opt:", hex(data[0]))
    print("data: ", data[1:len+1])


def moduleReadCmd(dev, opt, buf, len):
    data = bytearray(len + 1)
    i = 0
    while i < len:
        if i == 0:
            data[i] = 0x00 | opt
        else:
            data[i] = 0xff
        i = i + 1
    CS.low()
    dev.write_readinto(data, buf)
    CS.high()
    print("read opt:", hex(opt))
    print("data: ", buf[1:len+1])


def sendBuf(buf, sendLen):
    fifoStatus = bytearray(2)
    status = bytearray(2)
    moduleReadReg(module0, 0x17, fifoStatus)
    print("ffs:", hex(fifoStatus[1]))
    if ( (fifoStatus[1] & 0x20) == 0):
        moduleWriteCmd(module0, 0xb0, buf, sendLen)
        time.sleep_ms(10)
        if IRQ.value() == 0:
            moduleReadReg(module0, 0x07, status)
            if status[1] & 0x20:
                moduleWriteReg(module0, 0x07, 0x20)
                print("send ok")
    else:
        print("fifo is busy")


defaultAddrTx = bytes([0x02, 0x00, 0x00, 0x00, 0x00])
defaultAddrRx0 = bytes([0x02, 0x00, 0x00, 0x00, 0x00])
defaultAddrRx1 = bytes([0x01, 0x00, 0x00, 0x00, 0x00])
readAddr = bytearray(6)
sendData = bytes([0xAA, 0x55])
sendCnt = 0
reg = bytearray(2)
print("start")
moduleWriteReg(module0, 0x03, 0x03)                             #地址宽度设置为5字节
moduleReadReg(module0, 0x03, reg)
moduleWriteReg(module0, 0x02, 0x03)                             #使能接收数据管道0,1
moduleReadReg(module0, 0x02, reg)
moduleWriteCmd(module0, 0x20 | 0x10, defaultAddrTx, 5)          #设置发送端地址
moduleWriteCmd(module0, 0x20 | 0x0A, defaultAddrRx0, 5)         #设置接收管道0地址
moduleWriteCmd(module0, 0x20 | 0x0B, defaultAddrRx1, 5)         #设置接收管道1地址
moduleReadCmd(module0, 0x10, readAddr, 5)
moduleReadCmd(module0, 0x0A, readAddr, 5)
moduleReadCmd(module0, 0x0B, readAddr, 5)
moduleWriteReg(module0, 0x04, 0x03)                             #自动重发设置为250us，最大自动重发次数3次
moduleReadReg(module0, 0x04, reg)
moduleWriteReg(module0, 0x05, 0x02)                             #设置为第2信道，2402MHz
moduleReadReg(module0, 0x05, reg)
moduleWriteReg(module0, 0x06, 0x0E)                             #射频数据率2Mbps，TX发射功率7dBm
moduleReadReg(module0, 0x06, reg)
moduleWriteReg(module0, 0x07, 0x71)                             #清中断
moduleReadReg(module0, 0x07, reg)
moduleWriteReg(module0, 0x1D, 0x05)                             #使能动态负载长度，使能W_TX_PAYLOAD_NOACK
moduleReadReg(module0, 0x1D, reg)
moduleWriteReg(module0, 0x1C, 0x03)                             #使能接收管道0,1动态负载长度
moduleReadReg(module0, 0x1C, reg)
moduleWriteReg(module0, 0x00, 0x0A)                             #中断使能、开启CRC 1字节、开机处于发送模式
moduleReadReg(module0, 0x00, reg)

time.sleep_ms(2)
CE.high()
time.sleep_ms(2)
while True:
    print("send {0} times".format(sendCnt))
    sendBuf(sendData, 2)
    sendCnt = sendCnt + 1
    time.sleep_ms(1000)

'''

readReg = bytearray(2)
addr1 = bytearray(6)
addr2 = bytearray(6)
sendaddr = bytes([0xe5, 0xe5, 0xe5, 0xe5, 0xe5])
recvaddr = bytes([0xe7, 0xe7, 0xe7, 0xe7, 0xe7])
sendBuf = bytes([0x01, 0x02, 0x03, 0x04, 0x05, 0x06])

print("start")
time.sleep_ms(100)
moduleReadCmd(module0, 0x10, addr1, 5)
moduleWriteReg(module0, 0x03, 0x03)
moduleReadReg(module0, 0x03, readReg)

#moduleReadCmd(module0, 0x10, addr1, 5)
moduleWriteCmd(module0, 0x10 | 0x20, sendaddr, 5)
moduleReadCmd(module0, 0x10, addr1, 5)

moduleWriteCmd(module0, 0x0A | 0x20, recvaddr, 5)
moduleReadCmd(module0, 0x0A, addr2, 5)


#moduleReadReg(module0, 0x02, readReg)
#moduleReadCmd(module0, 0x0A, addr1, 5)
moduleWriteReg(module0, 0x02, 0x01)
moduleWriteReg(module0, 0x1D, 0x05)

moduleWriteReg(module0, 0x00, 0x0A)
#moduleReadReg(module0, 0x00, readReg)
time.sleep_ms(5)
CE.value(1)                             #进入发送模式
time.sleep_ms(5)
status = bytearray(2)
while True:
    moduleWriteCmd(module0, 0xB0, sendBuf, 6)
    print("send:",sendBuf)
    if 0 == IRQ.value():
        moduleReadReg(module0, 0x07, status)
        print("status: ", hex(status[1]))
    time.sleep_ms(500)
'''


'''
    status = bytearray(2)
    recvLen = bytearray(2)
    recvBuf = bytearray(32)
    if 0 == IRQ.value():
        moduleReadReg(module0, 0x07, status)
        if (status[0] & 0x40) == 0x40:
            moduleReadReg(module0, 0x11, recvLen)
            moduleReadCmd(module0, 0x61, recvBuf)
            print("recv: ", recvBuf)
            moduleWriteReg(module0, 0x07, 0x40)

    print("irq state:", IRQ.value())
    time.sleep_ms(500)
'''
